Hi all....
I am new memeber of tek-tips....
I am a beginner in VHDL and was thinking to create a 8 bit wide 16 bytes deep FIFO....and assign read pointer and write pointer and difference pointer.At reset the read and write pointers are zero...and to calculate the difference pointer when the data are stored and read out.
so...it would be great if u culd help me out to creeate this FIFO...
At every rising edge of the clock the read and write operations must occur.The status signals like fifofull,fifoempty can be used.I wuld appreciate a lot if u culd help me in this regard.
I am new memeber of tek-tips....
I am a beginner in VHDL and was thinking to create a 8 bit wide 16 bytes deep FIFO....and assign read pointer and write pointer and difference pointer.At reset the read and write pointers are zero...and to calculate the difference pointer when the data are stored and read out.
so...it would be great if u culd help me out to creeate this FIFO...
At every rising edge of the clock the read and write operations must occur.The status signals like fifofull,fifoempty can be used.I wuld appreciate a lot if u culd help me in this regard.
