VHDL counter problem

[uhuq]

Hi all,

I am trying to program a an atmel CPLD (ATF1508) in VHDL. The prochip software from atmel synthesising my VHDL code very well but its giving errors in fitting it on the chip.. saying its large design. I am sending you the code. The problem is in the Vector to integer conversion or integer to vector conversion. I wrote two functions for that.
I am doing it because I want to run a counter( 10 bit ) and generate addresses for the memory.
If I use a four bot counter than programs fits my code into the chip.Please advice!
Raza

library IEEE;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------------------------
Entity DPR is

port (
Data_bus2 ut bit_vector(7 downto 0);
Data_Bus : in bit_vector(7 downto 0); -- Right hand side of the memory data bus (8- bit)
Address_bus: out bit_vector(9 downto 0); -- Right hand side Address Bus
Read_write: out std_logic; -- Right hand side Read and Write Signals
Busy: inout std_logic; -- Right hand side Busy Signal
INT : in BIT; --Right hand side Intreupt Signal
Output_Enable : out std_logic; -- Output enable signal
Clk : in std_logic; --Clock Signal
latch : in std_logic;
CE: out std_logic
);
End DPR;
---------------------------------------------------------------------------------------------------------
Architecture DPR_ARCH of DPR IS -- Defining behaviour
TYPE s_type is (S0,S1,S2,S3,S4,S5,S6);
signal state, nxtstate : s_type;
Signal counter_var : bit_vector(0 to 9);
Signal read_var : bit_vector(7 downto 0);
--------------------Vector to Integer Function----------------------------------

FUNCTION vector_to_int(S : bit_vector( 0 to 9))
Return unsigned integer is
Variable result: unsigned integer := 0;
Begin
FOR i IN 0 to 8 LOOP
result := result * 2;
IF S(i) ='1' Then
result := result + 1;
End if;
End LOOP;
Return result;
End vector_to_int;

----------------Integer to Vector Function ------------------------------

FUNCTION integer_to_vector(int1, Nbits: unsigned integer)
Return bit_vector is
variable N1 : unsigned integer;
variable retval : bit_vector( Nbits-1 downto 0);

Begin
assert int1>=0;
N1 := int1;
FOR i IN retval' Reverse_Range Loop
if ( N1 mod 2) =1 THEN
retval(i) := '1' ;
Else
retval(i) := '0';
End if;
N1 := N1/ 2;
End LOOP;
Return retval;
End integer_to_vector;
--*****************************************************************
Begin
Process(state,INT,Clk)
Begin

If (state=S0) THEN
If (INT='0') Then
Read_write <='1';
CE <= '0';
Output_Enable <='0';
Address_bus<="1111111111";
read_var<= Data_Bus;
Data_bus2 <="11110000";
nxtstate<=S1;
End If;
End if;

If (state=S1) then
-- If ( read_var="00011111" ) Then
counter_var <="0000000111";
Data_bus2 <="00001111";
nxtstate<=S2;
-- End If;
End If;

If (state=S2) then
If (counter_var /= "0000000000") Then
counter_var<=integer_to_vector(vector_to_int(counter_var) -1,10);
Address_bus<=counter_var;
--Data_bus2 <="01111111";
nxtstate<=S2;
Else
nxtstate<=S3;
End If;
End If;

If ( state=S3) Then
If (counter_var="0000000001") Then
Read_write<='1';
CE<='1';
Output_Enable<='1';
Address_bus<="1111111111";
--Data_bus2 <="00000110";
nxtstate<=S4;
End If;
End If;

If (state=S4) Then
-- Data_bus2 <="00111110";
Read_write<='0';
CE<='0';
Output_Enable<='0';
nxtstate<=S0;
End If;

End Process;
------------------------------------------------------------------------------

PROCESS (Clk,state)

Begin
If (Clk'event AND Clk='1') Then --1
state <= nxtstate;
End if;
End PROCESS;
End DPR_ARCH ;

 

[teje]

Why you don't use the stardard function "to_integer" and
"to_unsigned". Normally, they are easilly implemented and synthesized.