VHDL assert problem

[janiaut]

hello everybody
Excuse me for my english,

I have a problem in VHDL
I seek how to especially use the asserts in a precise case. for those which do not know the assert is a little a débugger.
I have many signals has to test (to check the timings), I seek to analyze each signals and to check time at the high and low level during the simulation.
how then I to make.
For the moment I don't have tested
This is my code :

PROCESS (clk)
BEGIN
ASSERT ((phasebit'LAST_ACTIVE < (21*TIME_CLK_HDF) and (phase_clk = '1'))
REPORT "Phase_clk violation of the hold time"
SEVERITY Warning;

ASSERT ((phase_clk’Last_Event > (20*clk_hdf) and (phase_clk = '1'))
REPORT "Phase_clk violation of the High time"
SEVERITY Warning;
END PROCESS;

somebody could help me if it plait you it is rather urgent thank you for all