The only reference i was able to find:
If either controller is the active clock source, the network-clock PLL switch is thrown in the direction of the active clock. The system clock is recovered from the controller with the active clock source.
Tons of errors but getting no where with AT&T. My remote side is providing clock and this end is clocking off line but still I have problems on this end. The remote side has no errors and when At&t loops this end up, the errors go away.
Val.3662#sh controllers t1 3/1 brief
T1 3/1 is up.
Applique type is Channelized T1
Cablelength is short 133
Description: T1 to Las Vegas
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20000922, FPGA: 15
Framing is ESF, FDL is ansi & att, Line Code is B8ZS, Clock Source is Line Primary.
Current port master clock: recovered from controller 3/1
Data in current interval (156 seconds elapsed):
3187 Line Code Violations, 6368 Path Code Violations
145 Slip Secs, 0 Fr Loss Secs, 141 Line Err Secs, 2 Degraded Mins
116 Errored Secs, 115 Bursty Err Secs, 29 Severely Err Secs, 0 Unavail Secs
Update:
Opened a Cisco case on this and what they're telling me is that I need to separate the two VWICs into two different NM on the router. Apparently there is a design issue/limitation with these VWICs that has to do with the clock. I will post the result
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