Hello Alinmocanu,
If you want to synthesize VHDL you need a synthesizer tool.
There are some very good but very expensive tools for synthesis from for example Mentor Graphics such as Precision or from Synplify from synplicity. The drawback is that these tools are real professional tools and have a very high proce card attached.
Also synthesized VHDL code is actually not usable if you do not have another program to use it in. Synthesis of VHDL gives you a netlist (edif or some other format), this is just a summarry of generic logic your code requires, but you cannot put this in a pld. You need to implement it, this means mapping, placing and routing in Xilinx lingo or fitting in Altera lingo.
This is why I advise you to take a look at the following urls :
The links above are links to so called web packs.
The first one is a link to the download page of the Altera Quartus software webpack and the second one is a link to the download page of the Xilinx ISE webpack software.
Both programs are integrated design environments where you can write your VHDL code and synthesize and implement it to a downloadable bitfile or pof file for a PLD device.
Although these things are free they are rather useful for both vendors and act similar to the none free full licensed versions.
What program you choose is up to you, but of course if you are planning to do something with a Xilinx FPGA don't use Quartus and visa versa.
I do not know if other device vendors like latice have similar free versions of their design software, but I think that you can do a lot with the tools of the two major programmable logic vendors.
As I use both programs nearly every day (in the full versions) for professional reasons I can safely say that they both have their minor points but that they are generally spoken easy to use.
Regards and have fun
jeandelfrigo
