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Modeling a CLock in VHDL
- Thread starter mahal
- Start date
vhdlverilog
Technical User
hai mahal,
u just write this code
some signal is there of name clk
clk<=not(clk) after 5ns.
depending on the delay that u keep
u'r clock frequency depends on delay
dont forget to initialise the signal.
u just write this code
some signal is there of name clk
clk<=not(clk) after 5ns.
depending on the delay that u keep
u'r clock frequency depends on delay
dont forget to initialise the signal.
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