how to write a 16bit i/o register?

[samz]

i'm a newbie in vhdl, and i'm trying to write a 16 bit i/o register, but it is not working right. can someone help me solve it? I want to be able to write first then read, but it would only work if i read first and then write.
below is my code:

library ieee;
use iee.std_logic_1164.all

entity i/o_reg is
port (dataIn: in std_logic_vector (15 downto 0);
data: inout std_logic_vector (15 downto 0);
dataOut: out std_logic_vector (15 downto 0);
wr_l, rd_l: in std_logic);
end i/o_reg;

architecture model of i/o_reg is
begin
process (wr_l, rd_l) is
begin
if wr_l='0' then dataOut<=data;
elsif rd_l='0' then data<=dataIn;
end if;
end process;
end model;

 

[ahedin]

-- 1. If you want a register you need a clock. Unless you have a reason for
-- using a latch you probably want to use a register.
-- 2. Does your target device have internal 3-state buffers/lines (xilinx)?
-- If so, you can have one signal that is an input and an output.

------------------------------------------------------------------
-- unless you have tristate lines the output is always assigned
-- (it could be muxed with other 'dataOut' lines somewhere else)

library ieee;
use ieee.std_logic_1164.all;

entity io_reg is

port (dataIn : in std_logic_vector (15 downto 0);
dataOut : out std_logic_vector (15 downto 0);
wr_l, rd_l : in std_logic);

end io_reg;

architecture model of io_reg is

signal data_latch : std_logic_vector(dataIn'range) := (others => '0');

begin

dataOut <= data_latch;

process (rd_l) is
begin
if wr_l = '0' then
data_latch <= dataIn;
end if;
end process;

end model;

------------------------------------------------------------------
-- this uses a register
-- depending on your tools and target you may want a signal that simulates the
-- chip powering up and the initial value that is in your register
-- that is the RST signal below

library ieee;
use ieee.std_logic_1164.all;

entity io_reg2 is

port (RST : in std_logic; --configuration reset aka power up reset
CLK : in std_logic;
dataIn : in std_logic_vector (15 downto 0);
dataOut : out std_logic_vector (15 downto 0);
wr_l : in std_logic;
rd_l : in std_logic); --some people recommend/prefer one
--input/output per line

end io_reg2;

architecture model of io_reg2 is

signal data_register : std_logic_vector(dataIn'range);

begin

dataOut <= data_register;

process(RST,CLK)
begin
if RST = '1' then

data_register <= (data_register'range => '0');

elsif rising_edge(CLK) then

if wr_l = '0' then

data_register <= dataIn;

end if;
end if;
end process;

end model;

------------------------------------------------------------------
-- This uses a bus (which could be inside the chip or
-- outside of the chip.
--

library ieee;
use ieee.std_logic_1164.all;

entity io_reg3 is

port (RST : in std_logic;
CLK : in std_logic;
dataIO : inout std_logic_vector (15 downto 0);
wr_l : in std_logic;
rd_l : in std_logic);

end io_reg3;

architecture model of io_reg3 is

signal data_register : std_logic_vector(dataIO'range);

begin

--drive the bus when rd_l is asserted otherwise 3state.
dataIO <= data_register when rd_l = '0' else (others => 'Z');

process(RST,CLK)
begin
if RST = '1' then

data_register <= (data_register'range => '0');

elsif rising_edge(CLK) then

--something else should be driving the bus if the wr_l signal is active
if wr_l = '0' then

data_register <= dataIO;

end if;
end if;
end process;

end model;