In VHDL, if a signal is of integer data type, it is, by default, in the range -2**31 to 2**31, i.e., the signal will become a 32-bit wide bus.
If you want to specify a range, for example, you have a 4-bit positive counter, then you just have to define it as,
signal temp: integer range 0 to 15;
This assignment will assign a 40bit bus to the signal.