Hi All,
I am doing an FPGA Design where most of the VHDL code I am using is a reuse from another device (Designed by some other group who are not around).
In this code(s), there are a lot of signal assignments where the output of a block or even an internal used signal is not clocked. As a result, I am seeing glitches in the simulation using ModelSim tool.
Unfortunately, If I wanted to put these signals in clocked process for example (as a solution to the glitches), the timing where these signals are expected (from other places they are used) is messed up and as a result most of the code(s) don't work probably. Is there any way I can fix this. Fot example, is there anyway I can change below assignments without the need of putting them in a clocked process and hence introducing a delay.
cmp_rls <= STAT_DV and (STAT(0) or STAT(1));
data_end <= '1' when ( (data_byte_en/=(conv_std_logic_vector(0,data_byte_en'length)-1)) and DFIFO_DV='1') else '0';
Thanks in advance.
mmali69
I am doing an FPGA Design where most of the VHDL code I am using is a reuse from another device (Designed by some other group who are not around).
In this code(s), there are a lot of signal assignments where the output of a block or even an internal used signal is not clocked. As a result, I am seeing glitches in the simulation using ModelSim tool.
Unfortunately, If I wanted to put these signals in clocked process for example (as a solution to the glitches), the timing where these signals are expected (from other places they are used) is messed up and as a result most of the code(s) don't work probably. Is there any way I can fix this. Fot example, is there anyway I can change below assignments without the need of putting them in a clocked process and hence introducing a delay.
cmp_rls <= STAT_DV and (STAT(0) or STAT(1));
data_end <= '1' when ( (data_byte_en/=(conv_std_logic_vector(0,data_byte_en'length)-1)) and DFIFO_DV='1') else '0';
Thanks in advance.
mmali69