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Flip Flop Syncing
- Thread starter SteveD73
- Start date
stevieblunder
Technical User
A flip flop is implied when stuff is defined under a rising edge clock event.
I think the "sync" circuit you are thinking of is just two cascaded D Flip-flops. In VHDL thats just: asign under a clock event:
temp <= input;
out <= temp;
where temp and out are the outputs from the two FFs.
Sorry, I don't remember the exact VHDL syntax off the top of my head.
There is a extra clock delay. The idea is that the first FF should have settled any meta-stability before out is clocked, but really you are just making the odds very very high.
Steve
I think the "sync" circuit you are thinking of is just two cascaded D Flip-flops. In VHDL thats just: asign under a clock event:
temp <= input;
out <= temp;
where temp and out are the outputs from the two FFs.
Sorry, I don't remember the exact VHDL syntax off the top of my head.
There is a extra clock delay. The idea is that the first FF should have settled any meta-stability before out is clocked, but really you are just making the odds very very high.
Steve
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