enumeration types

[xyz987]

when I declare a new enumerated type, where shud I do it? before the architecture or b4 the entity definition or inside the architecture?

Thanks

 

[RVSachin]

Declarations are to be done after the 'architecture' and before the 'begin' for signals.

If the ports in your design are of enumerated data types, then the type declaration should be in a package visible to your design.

 

[xyz987]

I'm not sure if I have done the right thing. I have used a package in a sepearate file and complied it into work.

But I get error in the if statements. I used a case statement for it previously. that also was error.

can u pls check the code.
thanks.



library IEEE;
use IEEE.std_logic_1164.all;

package func_types is
type func_ops is (add, sub, mult, div);
end package func_types;

library IEEE;
use IEEE.std_logic_1164.all;
use work.func_types;

entity REAL_AU is

port ( x : in REAL;
y : in REAL;
func : in work.func_types.func_ops;
z : out REAL);
end entity REAL_AU;

architecture au_arch of REAL_AU is
begin

process
variable result : REAL;
begin
if ( func = add) then
result := x + y;
elsif ( func = sub ) then
result := x - y;
elsif ( func = mult ) then
result := x * y;
elsif ( func = div ) then
result := x/y;
end if;
z <= result after 10 ns;
end process;
end au_arch;

 

[RVSachin]

Hi,

I don't see anything wrong due to the package you have used. But, I see a compiler error in the last 'if' condition, where x is divided by y. Most of the synthesis tools support division operator '/' only when the divisor is a constant, and a power-of-2.

Since y in your case is not a power-of-2, it results in compiler error. Also, note that, generally, REAL data types aren't supported by synthesis tools either.