Hi all,
I am working on a VHDL code beautifier with Perl. I've come to this part of the beautification process and I got really stuck. Assume for example the following piece of VHDl code:
Well I'm trying to figure out the regular expressions to transform it to that:
Hence, briefly,
i. Place all words between 'port(' and ');' in columns.
ii. Separate
<signal_name_1>, <signal_name_2>,...,<signal_name_n> : <direction> <type>;
to
<signal_name_1> : <direction> <type>;
<signal_name_2> : <direction> <type>;
...
<signal_name_n> : <direction> <type>;
Any help, suggestion is more than welcomed
Thanks in advance!
I am working on a VHDL code beautifier with Perl. I've come to this part of the beautification process and I got really stuck. Assume for example the following piece of VHDl code:
Code:
entity JK_FF is
port( clock : in std_logic;
J, K : in std_logic;
reset : in std_logic;
Q, Qbar : out std_logic);
end JK_FF;
Well I'm trying to figure out the regular expressions to transform it to that:
Code:
entity JK_FF is
port( clock : in std_logic;
J : in std_logic;
K : in std_logic;
reset : in std_logic;
Q : out std_logic;
Qbar : out std_logic);
end JK_FF;
Hence, briefly,
i. Place all words between 'port(' and ');' in columns.
ii. Separate
<signal_name_1>, <signal_name_2>,...,<signal_name_n> : <direction> <type>;
to
<signal_name_1> : <direction> <type>;
<signal_name_2> : <direction> <type>;
...
<signal_name_n> : <direction> <type>;
Any help, suggestion is more than welcomed
Thanks in advance!