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VHDL

sheenjrg
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  • Question Question
Illegal LOC on symbol ...LOCed to GCLKIOB site
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2
Views
194
sheenjrg
sheenjrg
edhunter2003
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  • Question Question
Hi guys, when I try to do a post
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4
Views
226
VHDLguy
VHDLguy
sheenjrg
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Using wlf as input
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3
Views
325
sheenjrg
sheenjrg
naraic
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Modelsim
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11
Views
328
VHDLguy
VHDLguy
sheenjrg
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Adding Source
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3
Views
231
sheenjrg
sheenjrg
sheenjrg
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  • Question Question
Clock help
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4
Views
219
sheenjrg
sheenjrg
aryajur
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How to get a tristate condition
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1
Views
164
VHDLguy
VHDLguy
srikki9
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VHDL coding help
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7
Views
291
srikki9
srikki9
xyz987
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structural arch. for combinational ckt. - help pls.
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2
Views
121
VHDLguy
VHDLguy
naraic
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std_logic_vector divide
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7
Views
692
naraic
naraic
xyz987
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  • Question Question
Report at Exit
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3
Views
148
VHDLguy
VHDLguy
xyz987
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  • Question Question
trap exits in a process
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2
Views
165
xyz987
xyz987
xpp2000
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file I/O simulation
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1
Views
107
VHDLguy
VHDLguy
srikki9
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Problem with incrementing integer variable in VHDL
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0
Views
425
srikki9
srikki9
morem
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  • Question Question
Clock duty cycle
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2
Views
137
RVSachin
RVSachin
superosjecaj
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  • Question Question
bidirectional port
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1
Views
167
RVSachin
RVSachin
xyz987
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  • Question Question
enumeration types
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3
Views
191
RVSachin
RVSachin
PeggyYao
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  • Question Question
How to make process to execute when S'active?
Replies
1
Views
177
DigilogDesigner
DigilogDesigner
pinaki
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interfacing C with VHDL using the Scirocco simulator (Synopsys)
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0
Views
100
pinaki
pinaki
Prab
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  • Question Question
Vhdl process statement !
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0
Views
81
Prab
Prab
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