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Conversion program

Conversion program

Conversion program

(OP)
Hi,
I am currently writing a program to convert Verilog to VHDL using perl. Does anyone know how to get perl to pull certain words out of a string.
EG.
std_ulogic anyword [31:24;;

I need to pull anyword from the string and write it to a file.
Any help would be greatly appreciated.

RE: Conversion program

Perl has strong regex capabilities- but I have to admit I don't understand your example.
Say it a different way would you?

RE: Conversion program

(OP)
Sorry ,looking at it now that example is awfull. The following is an example of what I need to convert.
This=> input [31:24] rgf_bd_addr;
input rsm_vld_bit;
output r_data;

To This=> rgf_bd_addr : in std_ulogic_vector(31downto24);
rsm_vld_bit : in std_ulogic;
r_data : out std_ulogic;
Mike has been of great help with the output stuff so far, He produced the following code which works.
#!/usr/local/bin/perl
while(<>){
if(/^\s*output\s+(.*);\s*$/){
print "$1\t: out std_ulogic;\n";
}
}

RE: Conversion program

(OP)
Here is Mikes solution to the problem which works really well.

#!/usr/bin/perl
while(<>){
if(/^\s*output\s+(.*);\s*$/){
print "$1\t: out std_ulogic;\n";
}
if(/^\s*input.+(..):(..)]\s*(.*);\s*$/){
print "$3\t: std_ulogic_vector ($1 downto $2);\n";
}
}

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