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VHDL testbench

VHDL testbench

VHDL testbench

(OP)
I've been tasked with creating a sequence detector in vhdl and to create a testbench to verify my detector. I was able to create a testbench for the behavioral portion, but I'm stuck on how to create one for my dataflow portion (the logic equations of next state and output). The sequence is to detect '101110' including overlaps with an active low reset. I have broken down the next equations and output to be
Q1n <= (Q2 and Q3 and X) OR (Q1 and not Q3 and X);
Q2n <= (Q3 and not X) OR (Q1 and not X) OR (Q2 and not Q3 and X);
Q3n <= (not Q2 and X) OR (not Q3 and X);
Z <= (Q1 and Q3 and not X);

In my testbench I test for all combinations of Q1 Q2 Q3 and X and but still can't get my Z to output anything. My code is
library ieee;
use ieee.std_logic_1164.all;

entity detector is
port (CLK,nRST : in std_logic;
X : in std_logic;
Z : out std_logic
);
end entity;

architecture dataflow of detector is
signal Q1, Q2, Q3,Q1n,Q2n,Q3n: std_logic;
begin
Q1n <= (Q2 and Q3 and X) OR (Q1 and not Q3 and X);
Q2n <= (Q3 and not X) OR (Q1 and not X) OR (Q2 and not Q3 and X);
Q3n <= (not Q2 and X) OR (not Q3 and X);
Z <= (Q1 and Q3 and not X);

process(CLK)
begin
if nRST ='0' then
Q1 <='0';
Q2 <='0';
Q3 <='0';
elsif CLK='1' and CLK'event then
Q1n <= Q1;
Q2n <= Q2;
Q3n <= Q3;
end if;
end process;
end architecture;


my testbench code is
library ieee;
use ieee.std_logic_1164.all;

-- Add your library and packages declaration here ...

entity detector_dataflow_tb is
end detector_dataflow_tb;

architecture TB_ARCHITECTURE of detector_dataflow_tb is
-- Component declaration of the tested unit
component detector
port(
CLK : in STD_LOGIC;
nRST : in STD_LOGIC;
X : in STD_LOGIC;
Z : out STD_LOGIC );
end component;

-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal CLK : STD_LOGIC := '0';
signal nRST : STD_LOGIC := '1';
signal X : STD_LOGIC := '0';
-- Observed signals - signals mapped to the output ports of tested entity
signal Z : STD_LOGIC;

-- Add your code here ...
constant clk_period : time := 10ns;
signal Q1,Q2,Q3 : std_logic;
begin

-- Unit Under Test port map
UUT : detector
port map (
CLK => CLK,
nRST => nRST,
X => X,
Z => Z
);

-- Add your stimulus here ...
clk_process: process
begin
CLK <='0'; wait for clk_period/2;
CLK <='1'; wait for clk_period/2;
end process;

process
begin
nRST <= '0';
wait for 20 ns;
nRST <= '1';
X <= '0';
Q1<= '0';
Q2<= '0';
Q3<= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
Q2 <= '1'; Q3 <= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
Q1 <= '1'; Q2 <= '0'; Q3 <= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
Q2 <= '1'; Q3 <= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
X <= '1';
Q1<= '0';
Q2<= '0';
Q3<= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
Q2 <= '1'; Q3 <= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
Q1 <= '1'; Q2 <= '0'; Q3 <= '0';
wait for clk_period;
Q3 <= '1';
wait for clk_period;
Q2 <= '1'; Q3 <= '0';
wait for clk_period;
Q3 <= '1';
wait;
end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_detector_dataflow of detector_dataflow_tb is
for TB_ARCHITECTURE
for UUT : detector
use entity work.detector(dataflow);
end for;
end for;
end TESTBENCH_FOR_detector_dataflow;

If anyone can help me I would greatly appreciate it. My knowledge in VHDL is very limited.

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