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VHDL state machine

VHDL state machine

VHDL state machine

(OP)
Hi,
I created a state machine that initially reads the width and height values ​​of the image and the threshold of interest and saves them. Then the pixel-by-pixel image flows comparing each time the value read with the saved threshold and updating the "boundaries" of the area of ​​interest if necessary. Once the last pixel has been read, the length and height of the rectangle that surrounds the area of ​​interest of the image are known and the machine then calculates the area and saves it in memory.
By launching the "behavioral simulation" the machine behaves correctly with all the testbench supplied. Although it turns out to be also synthesizable, however, during the "post-synthesis functional simulation" the behavior is completely different from the expected one: in particular the computation starts already before receiving the reset and start signals, moreover the machine seems not to consider the clock in input, since in each cycle the value of mem_address is updated several times and not increased by one as expected.

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