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SLIP Error on Secondary Tie Link

SLIP Error on Secondary Tie Link

SLIP Error on Secondary Tie Link

(OP)
Hi!

We have this 2nd loop set up to cater additional 30 channel for the existing tie link which is connected with the same card (DPRI NTCk43AB) in option 61C. This was connected to a another cisco router. We do encounter slip error (dta300)on the new loop if it was clocking on the primary reference clock but not on the secondary meaning no slips on secondary clock. Telco provider said they haven't change anything on their end. Much help is appreciated.

As a work around, how can I make the sref clok to become the primary clock? like
pref ck0 0 will be pref CK0 1? thanks again

Here's our current configs:

FEAT syti

PREF CK0 0
SREF CK0 1
PREF CK1 0
SREF CK1 1

CCGD 15
CCAR 15
EFCS NO


SL-1 NETWORK TIMESLOT
B-CHANNEL 1 -15 1 -15 1 -15
16-30 17-31 17-31
D-CHANNEL 31 16 16
ssck 0

ENBL
CLOCK ACTIVE
SYSTEM CLOCK - TRACK ON LOOP 0
PREF - 0
SREF - 1
AUTO SWREF CLK - ENBL
NO ERROR
.ssck 1

ENBL
STANDBY
PREF - 0
SREF - 1
AUTO SWREF CLK - ENBL
NO ERROR

ADAN DCH 9
CTYP MSDL
DNUM 15
PORT 1
DES 29
USR PRI
DCHL 29
OTBF 32
PARM RS422 DTE
DRAT 64KC
CLOK EXT
NASA NO
IFC APAC
CNTY SING
SIDE USR
CNEG 1
RLS ID **
RCAP BRI
OVLR NO
OVLS NO
T310 10
INC_T306 2
OUT_T306 30
T200 3
T203 10
N200 3
N201 260
K 7

TIE LINK 2 (LOOP 28)
ADAN DCH 10
CTYP MSDL
DNUM 15
PORT 0
DES IBARV11
USR PRI
DCHL 28
OTBF 32
PARM RS422 DTE
DRAT 64KC
CLOK EXT
NASA NO
IFC APAC
CNTY SING
SIDE USR
CNEG 1
RLS ID **
RCAP BRI
OVLR NO
OVLS NO
T310 10
INC_T306 2
OUT_T306 30
T200 3
T203 10
N200 3
N201 260
K 7

LOOP 28
MFF CRC
ACRC YES
ALRM REG
RAIE NO
G1OS YES
SLP 5 24 H 30 1 H
BPV 128 122
CRC 201 97
FAP 28 1
RATS 10
GP2 20 100 S 12 S 12 S 4 S
MNG1 15 M
NCG1 15 M
OSG1 15 M
MNG2 15 S
NCG2 15 S
OSG2 15 S
PERS 50
CLRS 50
OOSC 5

LOOP 29
MFF CRC
ACRC YES
ALRM REG
RAIE NO
G1OS YES
SLP 5 24 H 30 1 H
BPV 128 122
CRC 201 97
FAP 28 1
RATS 10
GP2 20 100 S 12 S 12 S 4 S
MNG1 15 M
NCG1 15 M
OSG1 15 M
MNG2 15 S
NCG2 15 S
OSG2 15 S
PERS 50
CLRS 50
OOSC 5

E1 0/0/0 is up.
Applique type is Channelized E1 - balanced
Description: connection to BA PBX
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20100222, FPGA: 13, spm_count = 0
Framing is CRC4, Line Code is HDB3, Clock Source is Line.


E1 0/0/1 is up.
Applique type is Channelized E1 - balanced
Description: connection to BA PBX
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20100222, FPGA: 13, spm_count = 0
Framing is CRC4, Line Code is HDB3, Clock Source is Line.

RE: SLIP Error on Secondary Tie Link

(OP)
Guys we made some changes to clock to secondary reference clock on loop 1 and disable the pref clock. The slip is gone however after maybe 3-5 days, it tracks back to primary clock that is disabled. Need some help how to disable auto reference clock and is this advisable? thanks guys


ssck 0
DSBL

ENBL
CLOCK ACTIVE
SYSTEM CLOCK - TRACK ON LOOP 0
PREF - 0
SREF - 1
AUTO SWREF CLK - ENBL
NO ERROR
.trck sclk


.


DTI000
.ssck 1

ENBL
CLOCK ACTIVE
SYSTEM CLOCK - TRACK ON LOOP 1
PREF - 0
SREF - 1
AUTO SWREF CLK - ENBL (can i disable this and is it advisable?)
NO ERROR
.ssck 0

DSBL
.


DTI000

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