Hi everybody. I'm have to implement a testbench for a sign-mag adder in a college project, but im having problems.
I can do the analysis and the elaboration without any problems, however when i try to execute the file i receive the message "../../src/ieee/numeric_std-body.v93:1005:7:@0ms:(assertion warning): NUMERIC_STD.">": metavalue detected, returning FALSE"
Im new to vhdl, so i don't have any idea how to solve it.

The code of the testbench is:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY sign_mag_add_test IS
END sign_mag_add_test;
ARCHITECTURE arch OF sign_mag_add_test IS

SIGNAL a : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT sign_mag_add
PORT (
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1 : sign_mag_add
PORT MAP (
a => a,
b => b,
sum => sum
);
init : PROCESS
BEGIN
WAIT;
END PROCESS init;
always : PROCESS
BEGIN
a <= "0011"; b <= "0010";
wait for 200 ns;
a <= "0001"; b <= "0100";
wait for 200 ns;
a <= "1011"; b <= "0010";
wait for 200 ns;
a <= "0011"; b <= "1010";
wait for 200 ns;
a <= "1001"; b <= "0100";
wait for 200 ns;
a <= "0001"; b <= "1100";
wait for 200 ns;
a <= "1011"; b <= "0011";
wait for 200 ns;
a <= "0011"; b <= "1011";
wait for 200 ns;
wait;
WAIT;
END PROCESS always;
END arch;