can i assign signal in the following way??
can i assign signal in the following way??
(OP)
Hi,
I am new to vhdl and while coding i want to invert a cetain number of bits in a signal. the code is somewhat like this:
now i want to do something like this, the signal first_part in a previuos parts of the code copies a number of bits from an fpga stream, whose number of bits is variable but not more than 3. For example if the maximum number of bits are copied into first_part are 3, 001, in first case, in second case 01. however, the order of bits in first_part is inverted and 1 is missing. i.e the actual output for 001 is 1100, so i have to add 1 at the 4th position and also invert the order of 001 to 100. also for second case (01) the output should be 110 after attaching 1 at the third position.
the signal first_part contains the copied bits from the stream, signal flag contain the actual no bits, either 111 for 001 or 11 for 01 and signal second_part contains the final inverted form. Here, i want to ask that if the do the following, would it achieve my purpose without error:
I want to ask if this will in first case put value 1100 in second_part signal and in second case put value 110 in second_part?
Any help is appreciated.
I am new to vhdl and while coding i want to invert a cetain number of bits in a signal. the code is somewhat like this:
CODE --> vhdl
signal flag : STD_LOGIC_VECTOR(31 downto 0) := (others => '0') ; signal first_part : STD_LOGIC_VECTOR(31 downto 0) := (others => '0') ; signal second_part: STD_LOGIC_VECTOR(31 downto 0) := (others => '0') ;
now i want to do something like this, the signal first_part in a previuos parts of the code copies a number of bits from an fpga stream, whose number of bits is variable but not more than 3. For example if the maximum number of bits are copied into first_part are 3, 001, in first case, in second case 01. however, the order of bits in first_part is inverted and 1 is missing. i.e the actual output for 001 is 1100, so i have to add 1 at the 4th position and also invert the order of 001 to 100. also for second case (01) the output should be 110 after attaching 1 at the third position.
the signal first_part contains the copied bits from the stream, signal flag contain the actual no bits, either 111 for 001 or 11 for 01 and signal second_part contains the final inverted form. Here, i want to ask that if the do the following, would it achieve my purpose without error:
CODE --> vhdl
first_part(0) <= '1';-- because i want to attach the missing 1. --also first_part(31 downto 1) the signal contains bits "0000000000000000000000000000001" and corresponding flag signal wud be "0000000000000000000000000000111" second_part(31 downto 4) <= "0000000000000000000000000000"--padding with zeros bc max number of bits to be used for this signal are 4. second_part(3 downto 0)<= first_part(0 to 3) if flag(2)='1' or '0' & first_part(0 to 2) if flag(1)='1' or "00" & first_part(0 to 1) if flag(0)='1' or "000" & first_part(0) if flag(0)='0';
I want to ask if this will in first case put value 1100 in second_part signal and in second case put value 110 in second_part?
Any help is appreciated.
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