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I am getting the following message and i wish to remove this:

\o Verilog *W,MOREBITS: Net 'vdd!' has width (1) which is more than of instance/terminal
\o 'V1' width (1)
\o Verilog *W,MOREBITS: Net 'gnd!' has width (1) which is more than of instance/terminal
\o 'V1' width (1)

the verilog code is:
//Verilog HDL for "worklib", "top" "verilog"

`timescale 1ns/1ns

module top2;

wire [1:0] n;
reg [1:0] m;

initial m = 2'b00;
always #10 m = m + 2'b01;

test2_shell A (.i_1(m[1]), .i_0(m[0]), .o_1(n[1]), .o_0(n[0]));

vsource #(.dc(5.0), .type("dc")) V1 (cds_globals.\vdd! , cds_globals.\gnd! );


//Verilog HDL for "worklib", "test2_shell" "verilog"

module test2_shell ( o_0, o_1, i_0, i_1 );
output o_1, o_0;
input i_1, i_0;

test2 U1 (o_0, o_1, i_0, i_1);


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