Log In

Come Join Us!

Are you a
Computer / IT professional?
Join Tek-Tips Forums!
  • Talk With Other Members
  • Be Notified Of Responses
    To Your Posts
  • Keyword Search
  • One-Click Access To Your
    Favorite Forums
  • Automated Signatures
    On Your Posts
  • Best Of All, It's Free!
  • Students Click Here

*Tek-Tips's functionality depends on members receiving e-mail. By joining you are opting in to receive e-mail.

Posting Guidelines

Promoting, selling, recruiting, coursework and thesis posting is forbidden.

Students Click Here


compare 2's complement in verilog

compare 2's complement in verilog

compare 2's complement in verilog

I am now converting my design to 2's complement, and I am having trouble using the compare operator with the assign command.

wire w7;
assign w7 = (Vout > Vpeak)? 1 : 0;

Vpeak will NEVER go below zero so I was going to write an if statement saying the following:

always @ (Vout or Vpeak)
assign w7 = 0;
assign w7 = (Vout > Vpeak)? 1 : 0;

With this change I get an error stating "Reference to scalar wire 'w7' is not a legal reg or variable lvalue"

Do you have any advice?

Red Flag This Post

Please let us know here why this post is inappropriate. Reasons such as off-topic, duplicates, flames, illegal, vulgar, or students posting their homework.

Red Flag Submitted

Thank you for helping keep Tek-Tips Forums free from inappropriate posts.
The Tek-Tips staff will check this out and take appropriate action.

Reply To This Thread

Posting in the Tek-Tips forums is a member-only feature.

Click Here to join Tek-Tips and talk with other members!

Close Box

Join Tek-Tips® Today!

Join your peers on the Internet's largest technical computer professional community.
It's easy to join and it's free.

Here's Why Members Love Tek-Tips Forums:

Register now while it's still free!

Already a member? Close this window and log in.

Join Us             Close