×
INTELLIGENT WORK FORUMS
FOR COMPUTER PROFESSIONALS

Contact US

Log In

Come Join Us!

Are you a
Computer / IT professional?
Join Tek-Tips Forums!
  • Talk With Other Members
  • Be Notified Of Responses
    To Your Posts
  • Keyword Search
  • One-Click Access To Your
    Favorite Forums
  • Automated Signatures
    On Your Posts
  • Best Of All, It's Free!

*Tek-Tips's functionality depends on members receiving e-mail. By joining you are opting in to receive e-mail.

Posting Guidelines

Promoting, selling, recruiting, coursework and thesis posting is forbidden.

Students Click Here

Cannot run Post-Fit simulation

Cannot run Post-Fit simulation

Cannot run Post-Fit simulation

(OP)
Hi all

I am very new to VHDL :)

I am trying to write a simple program, and when i run the Behavioral simulation it all looks good, and i perform the way it should...

but i dont get any result when i run the Post-Fit simulation.

these are the errors i get:
ERROR:Simulator:37 - Sdf root module /UUT/ specified does not exist in the


and this is the Warnings:
WARNING:HDLParsers:3583 - File "N:/J.30/env/TOS/HDLPkgs/vhdl/vital2000/restricted/timing_b.vhd" which file "C:/Xilinx91i/vhdl/src/simprims/simprim_Vcomponents.vhd" depends on is modified, but has not been compiled.  You may need to compile "N:/J.30/env/TOS/HDLPkgs/vhdl/vital2000/restricted/timing_b.vhd" first.
WARNING:Simulator:273 - Default port map for entity sds to component sds connects OUT mode local port StepMotorA of the component to INOUT mode port of the entity.
WARNING:Simulator:273 - Default port map for entity sds to component sds connects OUT mode local port StepMotorB of the component to INOUT mode port of the entity.
WARNING:Simulator:425 - No default binding for component sds. Port Frem is not on the entity.
WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst test1/UUT
WARNING:Simulator:144 - Cannot find block UUT/.


this is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sds is
    Port ( Frem, Tilbage, clock : in  STD_LOGIC;
            Q : inout std_logic_vector(1 downto 0) := "00";
            C : inout std_logic := '1';
           StepMotorA, StepMotorB : out  STD_LOGIC);
end sds;

architecture Behavioral of sds is

begin
state : process(clock) is
    begin
        if clock'event and clock = '1' then

                    C <= not(C);
                    if (C = '0') then Q(0) <= not(Q(0)); end if;
                    if (C = '1') then Q(1) <= not(Q(1)); end if;

        end if;
    
    end process state;
    StepMotorA <= Q(0);
    StepMotorB <= Q(1);
end Behavioral;


 btw. the chip i want to program is a CX9536
many thanks
Andreas Nordbek

Red Flag This Post

Please let us know here why this post is inappropriate. Reasons such as off-topic, duplicates, flames, illegal, vulgar, or students posting their homework.

Red Flag Submitted

Thank you for helping keep Tek-Tips Forums free from inappropriate posts.
The Tek-Tips staff will check this out and take appropriate action.

Reply To This Thread

Posting in the Tek-Tips forums is a member-only feature.

Click Here to join Tek-Tips and talk with other members! Already a Member? Login

Close Box

Join Tek-Tips® Today!

Join your peers on the Internet's largest technical computer professional community.
It's easy to join and it's free.

Here's Why Members Love Tek-Tips Forums:

Register now while it's still free!

Already a member? Close this window and log in.

Join Us             Close