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VHDL Case statement syntax?

VHDL Case statement syntax?

VHDL Case statement syntax?

(OP)
I am trying to write code to emulate the 8051 microcontroller.  I am modeling the control unit as a giant state machine and I was wondering if some of the case statement syntax I'm using is correct/valid/reasonable.

First of all, is a case within a case statement valid?  Second, when I look at the Op Code, can I use the case statment I am using to execute the same code for when the high nibble is 2, 3, 4, 5, 6, or 9?  (Will the statements at the end only execute if the high nibble is 9 and not the others?).  Please advise, thanks.

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   case state is
    when Fetch => IR <= ROM_IN;
                  PC <= PC + 1;
                  state <= Decode;

    when Decode => If (IR(3 downto 0) = "0000") then
                    State <= Exe_Jump;
                   Else
                    case IR(7 downto 4) is
                     when "0010" =>
                     when "0011" =>
                     when "0100" =>
                     when "0101" =>
                     when "0110" =>
                     when "1001" =>
                      state <= Exe_ALU;
                     when "0111" =>
                      state <= Exe_MOV_Imm;
                     when "1101" =>
                      state <= Exe_DJNZ;
                     when others =>
                      state <= Fetch;
                    end case;
                   End if;

...
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