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Yet another CC question 2

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M1north

IS-IT--Management
Sep 28, 2007
357
CA
I have a OPT61c running 25.13. It will not switch clocks when you attempt to do so in LD 60.

However, when you swap CPU the clocks change and stay with the active core. I tried replacing the CC but it still gives me the same error, DTI, when I try to swap in LD 60.

My question is has anyone seen this before and why is the CC swapping with the active core?

Thx
 
have you verified the cabling? also, verify the proper card slots are used...
 
Clocks are in proper slots....are you speaking of the cabling between clocks or the pri/sec reference cables?
 
M1, yes, all of the cables between the clocks and into the PRI cards.. just to verify.
 
Hey guys, here is exactly what happens:

CONNECT 9600/ARQ/V34/LAPM/V42BIS

OVL000
>ld 60
DTI000
.ssck 0
ENBL
STANDBY
SYSTEM CLOCK - TRACK ON LOOP 27
PREF - 27
SREF - 3
AUTO SWREF CLK - ENBL
NO ERROR
.ssck 1
ENBL
CLOCK ACTIVE
SYSTEM CLOCK - TRACK ON LOOP 27
PREF - 27
SREF - 3
AUTO SWREF CLK - ENBL
NO UART
.
DTC001


DTI000
.swck
0
DTI010


.****
OVL000
>ld 135
CCED000
.stat cpu
cp 1 15 PASS NORMAL ENBL

cp simm/bank stat
1 0/0 ENBL
1 1/0 ENBL


cp 0 15 PASS NORMAL STDBY

cp simm/bank stat
0 0/0 ENBL
0 1/0 ENBL
.scpo*
CCED000
.scpu
OK
.
ERR020 26 0 0

XMI000 4 : PLL UNLOCK EVENT

XMI000 12 : PLL UNLOCK EVENT

XMI000 20 : PLL UNLOCK EVENT

XMI000 28 : PLL UNLOCK EVENT

CCED762 SWO 0: Graceful switch-over to side 0 completed
Previous Graceful SWO: at 3/11/08 20:59:21

CCED000
.
CCED000
.scpu
OK
.
ERR020 2 0 2

XMI000 4 : PLL UNLOCK EVENT

XMI000 12 : PLL UNLOCK EVENT

XMI000 20 : PLL UNLOCK EVENT

XMI000 28 : PLL UNLOCK EVENT

CCED762 SWO 1: Graceful switch-over to side 1 completed
Previous Graceful SWO: at 3/11/08 21:03:34

CCED000
.ssck 0
CCED001 Invalid command.
.****
>ld 60
DTI000
.ssck 0
ENBL
STANDBY
SYSTEM CLOCK - TRACK ON LOOP 27
PREF - 27
SREF - 3
AUTO SWREF CLK - ENBL
NO ERROR
.ssck 1
ENBL
CLOCK ACTIVE
SYSTEM CLOCK - TRACK ON LOOP 27
PREF - 27
SREF - 3
AUTO SWREF CLK - ENBL
NO ERROR
.swck
0
DTI010


.****
OVL000
 
Ok, I`m starting to think its not the clocks....

ERR0020 l s c Input message received from unequipped PE pack l s c. No data exists for any
TN on this pack, which is disabled to prevent further input.
If all messages from same pack or from same PE shelf. Suspect:
PE pack l s c (if present)
Peripheral buffer on loop l shelf s
Network loop s
ERR
Page 450 of 1250 ERR: Error Monitor (Hardware)
553-3001-411 Preliminary 8.01 June 2000
ERR
Cables connecting network and peripheral shelves
Other PE packs on loop l shelf s connectors
If all messages from loop L (various shelves). Suspect:
1. Network loop l or associated cables or connectors
2. Any peripheral buffer pack on loop l.
For SL-1 XN: Messages occur only when a specific System Clock Generator
(SCG) is providing clock and loops in all groups are affected. Suspect:
1. QPC411 SCG providing clock when messages occur
2.Any QPC412 Intergroup Switch (IGS).
Messages occur only when a specific SCG is providing clock and loops on both
shelves of one group are affected. Suspect:
1. QPC412 IGS associated with affected group when messages occur
2. Cable connecting the SCG and IGS packs via the Junctor
********************************************************
Messages are all from loops on the same network shelf. Suspect:
1. Peripheral signaling pack on affected shelf -jackpot?
2. QPC412 IGS on affected shelf -OPT61 - so not this...
3. Any network, conference or TDS pack on this shelf - maybe?

***I am also getting TDS514 on loop 12 for the last month. I tried replacing this card and the errors would not go away

***********************************************************
Messages occur only when a specific CPU is active and only one group is
affected. Suspect:
CE Extender connecting CPU to affected group, or
interconnecting cables.
If all messages are from the same XMLC/XDLC,
 
OK, so after swapping the CPU last night a few times I came in to see LOOP 4 0 having issues on multipe cards. I disabled the loop, re-seated the comntroller card and the loop came up working good.

I really need to figure this one out now...

Thx for any help.
 
Here`s the log from last night:

DROL000 DAILY ROUTINE BEGIN
NWS LD30 BEGIN 23:00 3/11/2008

NWS142 0

NWS301 4 0 : -1 -3 -4 -8 -9 -10 -11 -12 -13 -14 -15

NWS301 12 0 : -0 -2 -3 -4 -5 -7 -8 -10 -11 -12

NWS301 20 0 : -1 -2 -3 -11 -15

DROL001 DAILY ROUTINE END
NWS LD30 END 23:02 3/11/2008

DROL000 DAILY ROUTINE BEGIN
TDS LD34 BEGIN 23:02 3/11/2008

DTC001

TDS511 004 0 15 0 1

TDS511 004 0 15 0 2

TDS511 004 0 15 0 3

TDS508 004 0 15 0

TDS320 004 0 15 0

TDS511 004 0 15 1 1

TDS511 004 0 15 1 2

TDS511 004 0 15 1 3

TDS508 004 0 15 1

TDS320 004 0 15 1

TDS511 004 0 15 2 1

TDS511 004 0 15 2 2

TDS511 004 0 15 2 3

TDS508 004 0 15 2

TDS320 004 0 15 2

TDS511 004 0 15 3 1

TDS511 004 0 15 3 2

TDS511 004 0 15 3 3

TDS508 004 0 15 3

TDS320 004 0 15 3

TDS511 004 0 15 4 1

TDS511 004 0 15 4 2

TDS511 004 0 15 4 3

TDS508 004 0 15 4

TDS320 004 0 15 4

TDS511 004 0 15 5 1

TDS511 004 0 15 5 2

TDS511 004 0 15 5 3

TDS508 004 0 15 5

TDS320 004 0 15 5

TDS511 004 0 15 6 1

TDS511 004 0 15 6 2

TDS511 004 0 15 6 3

TDS508 004 0 15 6

TDS320 004 0 15 6

TDS511 004 0 15 7 1

TDS511 004 0 15 7 2

TDS511 004 0 15 7 3

TDS508 004 0 15 7

TDS320 004 0 15 7

TDS514 012 0 15 7 1

TDS514 012 0 15 7 1

TDS514 012 0 15 7 1

TDS514 012 0 14 7 1

DROL001 DAILY ROUTINE END
TDS LD34 END 23:06 3/11/2008

DROL000 DAILY ROUTINE BEGIN
CNF LD38 BEGIN 23:06 3/11/2008

DROL001 DAILY ROUTINE END
CNF LD38 END 23:06 3/11/2008

DROL000 DAILY ROUTINE BEGIN
BCD LD45 BEGIN 23:06 3/11/2008

DROL001 DAILY ROUTINE END
BCD LD45 END 23:09 3/11/2008

DROL000 DAILY ROUTINE BEGIN
DTIM LD60 BEGIN 23:09 3/11/2008

DROL001 DAILY ROUTINE END
DTIM LD60 END 23:09 3/11/2008

DROL000 DAILY ROUTINE BEGIN
CCED LD135 BEGIN 23:09 3/11/2008

DROL001 DAILY ROUTINE END
CCED LD135 END 23:09 3/11/2008

ERR020 3 0 0

XMI000 4 : PLL UNLOCK EVENT

XMI000 12 : PLL UNLOCK EVENT

XMI000 20 : PLL UNLOCK EVENT

XMI000 28 : PLL UNLOCK EVENT

AUD000

CCED762 SWO 0: Graceful switch-over to side 0 completed
Previous Graceful SWO: at 3/11/08 21:04:13

TIM000 23:15 3/11/2008 CPU 0

DTC001

DTC001

AUD000

DTC001

TIM000 00:00 4/11/2008 CPU 0

DTC001

AUD000

DTC001

DTC001

AUD000

DTC001

TIM000 01:00 4/11/2008 CPU 0

AUD000

DTC001

DTC001

AUD000

DTC001

DTC001

AUD000

TIM000 02:00 4/11/2008 CPU 0

DTC001

DTC001

AUD000

DTC001

DTC001

AUD000

TIM000 03:00 4/11/2008 CPU 0

DTC001

DTC001

AUD000

DTC001

DTC001

AUD000

TIM000 04:00 4/11/2008 CPU 0

DTC001

DTC001

AUD000

DTC001

AUD000

DTC001

TIM000 05:00 4/11/2008 CPU 0

DTC001

AUD000

DTC001

DTC001

AUD000

DTC001

TIM000 06:00 4/11/2008 CPU 0

DTC001

AUD000

DTC001

DTC001

AUD000

ERR4019 2146

TIM000 06:44 4/11/2008 CPU 0

ERR4019 2515

ERR4019 3237

DTC001

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

ERR020 4 0 11

TIM000 06:59 4/11/2008 CPU 0

TIM000 07:00 4/11/2008 CPU 0

ERR4019 3072

DTC001

AUD000

TIM000 07:15 4/11/2008 CPU 0

DTC001

DTC001

AUD000

DTC001

TIM000 08:00 4/11/2008 CPU 0

DTC001

AUD000

DTC001

AUD000

DTC001

DTC001

AUD000

TIM000 09:00 4/11/2008 CPU 0

DTC001

ERR020 4 0 9

ERR020 4 0 11

ERR020 4 0 9

ERR020 4 0 12
 
Also found:

.stat
004 0 15 7 DTR
004 0 15 6 DTR
004 0 15 5 DTR
004 0 15 4 DTR
004 0 15 3 DTR
004 0 15 2 DTR
004 0 15 1 DTR
004 0 15 0 DTR
.enl
.
TDS203
4
.
TDS203
enll 4
LOOP NOT TDS
.enlr 4 0 15

XMI001 4 0 15 XDTR

XMI002 4 0 15 XDTR
TDS320
004 0 15 0 DTR OK
004 0 15 1 DTR OK
004 0 15 2 DTR OK
004 0 15 3 DTR OK
004 0 15 4 DTR OK
004 0 15 5 DTR OK
004 0 15 6 DTR OK
004 0 15 7 DTR OK
 
I guess nobody wants to touch this one....so I will start by replacing the controller card on loop 4, then the network card, then the persig card on shelf 0.

Let me know if anyone has any other ideas...

Thx
 
This issue has been resolved by replacing the cable between the two clocks and by replacing the controller card on superloop 4.

Thanks for all the replies.
 
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