jonythewalker
Programmer
is it possible to synthesis of VHDL module if there is integer variables in the VHDL module ?
Tek-Tips is the largest IT community on the Internet today!
Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!
-
Congratulations Chriss Miller on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!
synthesis of VHDL module
- Thread starter jonythewalker
- Start date
- Status
jeandelfrigo
Programmer
Hi,
Use of variables in code intended for sysnthesis is not advised.
Regards,
jeandelfrigo
Use of variables in code intended for sysnthesis is not advised.
Regards,
jeandelfrigo
- Thread starter
- #3
- Status