SPI interface

[Renniks51]

Hello all, I designing an SPI interface between an FPGA and a audio reciever IC. In order for the information to be passed correctly, the data has to be transmitted exactly when the Word Clock (ILRCK_i) toggles. Thus far I have not been able to accomplish this, I lose 2 to 3 clock cycles before things start to transmit. I would be grateful for any help I could receive.


Data_out: process(RESET, ILRCK_i, ISCLK_i)
begin
ILRCK_o <= ILRCK_i;
ISCLK_o <= ISCLK_i;

if(RESET = '1')then
ILRCK_o <= '0';
ISCLK_o <= '0';
SD_out <= '0';
counter_l <= 0;
counter_r <= 0;
SD_L_tmp <= ZERO;
SD_R_tmp <= ZERO;
flag_R <= '0';
flag_L <= '0';


elsif(ISCLK_i'event and ISCLK_i = '1')then
counter_r <= counter_r + 1;
counter_l <= counter_l + 1;

case ILRCK_i is

when '0' =>
SD_out <= SD_R_tmp(max_val);
counter_L <= 0;
if(flag_R = '0')then
SD_R_tmp <= SD_R;
flag_R <= '1';
else
flag_L <= '0';
if(counter_r >= max_val+1)then
SD_R_tmp <= ZERO;
counter_r <= 0;
else
SD_R_tmp <= SD_R_tmp((max_val -1)downto) & '0';

end if;

end if;


when '1' =>
SD_out <= SD_L_tmp(max_val);
counter_r <= 0;
if(flag_L = '0')then
SD_L_tmp <= SD_L;
flag_L <= '1';
else
flag_R <= '0';
if (counter_l >= max_val + 1)then
SD_L_tmp <= ZERO;
counter_l <= 0;
else
SD_L_tmp <= SD_L_tmp((max_val -1) downto 0) & '0';

end if;

end if;

when others =>
counter_l <= 0;
counter_r <= 0;



end case;

end if;



end process;

 

[Renniks51]

I figured it out, here is what I did for all of you who are curious


architecture cirrus_spi_trans_a of cirrus_spi_trans is
signal SD_L_shift :std_logic_vector(max_val downto 0); --shift register for left channel
signal SD_R_shift :std_logic_vector(max_val downto 0); --shift register for right channel

signal SD_tmp :std_logic_vector(max_val downto 0);
signal SD_L_tmp :std_logic_vector(max_val downto 0); --temp register for left channel
signal SD_R_tmp :std_logic_vector(max_val downto 0); --temp register for right channel
constant ZERO : std_logic_vector(max_val downto 0) := "000000000000000000000000";


begin

----------------------------------------------------------------------------------------------------------------------------
--this process takes two channels of data (left & right) and serially transfers it to a shift register by use of two clocks
----------------------------------------------------------------------------------------------------------------------------

Data_out: process(RESET, ILRCK_i, ISCLK_i)
begin

ILRCK_o <= ILRCK_i;
ISCLK_o <= ISCLK_i; --async reset


if(RESET = '1')then
sd_L_shift <= ZERO;
SD_R_shift <= ZERO;
ILRCK_o <= '0';
ISCLK_o <= '0';
SD_tmp <= ZERO;
SD_L_tmp <= ZERO;
SD_R_tmp <= ZERO;



elsif(ISCLK_i'event and ISCLK_i = '1')then --when master clk tics

SD_L_tmp <= SD_L; --left channel data put into temp register
SD_R_tmp <= SD_R; --right channel data put into temp register
SD_R_shift <= SD_R_shift((max_val -1) downto 0) & '0'; --right channel shift register shifts
SD_L_shift <= SD_L_shift((max_val -1) downto 0) & '0'; --left channel shift register shifts


case ILRCK_i is
when '1' => --when word clk is 1

SD_R_shift <= SD_R_tmp; --right temp register moved into right shift register

when '0' => --when word clk is 0
SD_L_shift <= SD_L_tmp; --left temp register moved into left shift register
when others =>

end case;

end if;



end process;

--------------------------------------------------------------------------
--This Process assigns the SD_out output in sync with word clk-----------
--------------------------------------------------------------------------

SD_Out_p: process(ILRCK_i, SD_L_shift, SD_R_shift)
begin

if(ILRCK_i = '1')then
SD_out <= SD_L_shift(max_val);

else
SD_out <= SD_R_shift(max_val);

end if;

end process;

end cirrus_spi_trans_a;