Segmented addressing

[xwb]

When the 386 came out it boasted to have a linear addressing range of 4G and a segmented addressing range of 64Tb. Just wondering: are there any OSs/hardware that take advantage of the 64Tb addressing on 386s and Pentiums?

Intel has done a lot of work to put this feature in but does anyone use it?

We're being sold core 2s and core 7s which support 64 bit addressing but a simple 386 could have done that using segmented addressing. Is segmented addressing too difficult? (Windows 3.x survived with the 16 bit variant)

 

[Noway2]

From what I remember, there was a limitation is in the number of address lines that are brought out of the processor and routed through the motherboard to the memory devices. While the theoretical support was for 64Tb, this would have been usable as virtual memory, not physical memory. With virtual memory, a program that is running in the lower range of real memory would intercept the page fault signal and map the high memory to and from the hard drive.

I also remember that there were two versions of the 386, the SX and DX and that these suffix designations didn't refer to the presence of a co-processor. The SX had a 32 bit instruction set, but only a 16 bit wide bus. Consequently, it could run "32 bit" applications, but needed to do extra bus cycles. The DX had the full 32 bit bus.

A 32 bit address (lines) gives a range of 4Gb of physical address range. To get 64Tb of address range would require 46 address lines. I don't think the 386 had this many address lines.