problems with instance

[debita]

Hi! My problem is this:

I've programmed a register, made by JK flip-flops, and now I want to instance that register to build a bench of registers. The problem is that I need 2 read outputs, and I don't know if it is possible in the generate to associate the Q output of my register to this two outputs of the bench. Sorry for my English

 

[jeandelfrigo]

debita,

I don't know if I understand the problem or question correclty but I'll try.

So basically you have this, for simplicity I'll replace the J_K FF by a simple D flip flop.
I've also skipped resets for simplicity.

file A :

entity DFF is
port (
clk : in std_logic;
D : in std_logic;
Q : out std_logic
);
end DFF;

architecture RTL of DFF is
begin
process(clk)
if (clk'event and clk = '1')then
Q <= D;
end if;
end process;

end RTL;

Now you want to instantiate this flip flop several times in another file and interconnect the different instances ?

entity top is
port (
clk : in std_logic;
Din : in std_logic
end top;

architecture blabla of top is
component DFF
port (
clk : in std_logic;
D : in std_logic;
Q : out std_logic
);
end component;

signal clk : std_logic;
signal Q1 : std_logic;
signal Q2 : std_logic;
signal Q3 : std_logic;
signal Q4 : std_logic;
signal Q5 : std_logic;

begin
i_DFF1 : DFF
port map (
clk => clk,
D => Din,
Q => Q1
);

i_DFF2 : DFF
port map (
clk => clk,
D => Q1,
Q => Q2
);

i_DFF3 : DFF
port map(
clk => clk,
D => Q2,
Q => Q3
);

i_DFF4 : DFF
port map(
clk => clk,
D => Q2,
Q => Q4
);

i_DFF5 : DFF
port map (
clk => clk,
D => not Q1,
Q => Q5
);

E <= Q2 and not Q3 or Q4;

end blabla;

So this is an example of how to instantiate multiple instances of the same component and how to interconnect the instances to each other. It shows that you can use the output of one instance as input for multiple other instances
not necessarily of the same type of instance. You can even use the outputs in concurrent statements. Note that modelsim doesn't like the not Q1 statement in the port map. You need to do the inversement in a separate concurrent statement for modelsim, but for most compilers the inversion in the port map is no problem.

So basically you should see the instances as IC's on a PCB and you use the signals in the upper level file as wire to interconnect then. The only thing is every wire needs to have a unique name, else it would be the same wire. But you can connect the same wire to several different pins of the ICs (= instances). The only thing you cannot do unpunished is connecting two (or more) outputs of different instances with the same wire (signal). You wouldn't want to do that on a PCB as well.

I hope this has explained and helped you in some way.
If not please clarify your problem a little so I can better understand it and maybe help you out (further).

regards

jeandelfrigo