Franklin97355, Wahnula, and BigBadBen – Many thanks!
The plot thickens ... not ddr ... double-sided ... now just HD to clarify!
Obtained varying data on each stick …
Beating about in the dark …
Did search on “density” … only registered with Samsung …
Problem is … not quite sure what I’m looking for … or how to interpret it when I find it??
May be the answer lies in the soil ...
Whatever, here is some data, which hopefully might hold some clues???
a) Samsung 256 MB 133Mhz SDRAM PC133 DIMM 256MB 168PIN
M390S1723BT1-C75
•Organization : 16MX72
•Composition : 16MX8 * 9ea
•Used component part # : K4S280832B-TC75
•# of banks in module : 1 Row
•# of banks in component : 4 banks
•Feature : 1,500 mil height & double sided component
•Refresh : 4K/64ms
Module Row density 1 Row of 128MB 20h
Module Row density 1 Row of 256MB 40h
Module Row density 2 Rows of 128MB 20h
Module Row density 2 Rows of 256MB 40h
b) Micron 512 MB 133Mhz SDRAM PC133 DIMM 512MB 168PIN
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Is any of this information definitive, please?
Does “Fully synchronous; all signals registered on positive
edge of system clock” suggest both sides will be read … or is that just wishful thinking?
Once again, many thanks,
Eponymous