<<Does someone know how can I write a generic package (using the generic keyword) in order to pass an integer (for example) to the package upon usage? I know it's possible in Ada, but didn't find it in the books I have about VHDL>>
Packages do not have generics. Only entities may have generics. You can however, have deferred constants that are elaborated during the simulation of the design.
Deferred constants are not synthesizable.
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Ben
vhdlcohen@aol.com Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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