jhall01,
You are correct in this case. However, I just wanted to point out that the FSB doesn't control the memory bus. The FSB only concerns the connection between the CPU and the chipset - memory has its own connection. Back in the day of the Pentium and Pentium II, the FSB and memory bus were locked at the same speed to simplify things. Newer boards have a separate setting for the memory bus, which is now totally independent.
Do you remember the first P4's that used PC-133 SDRAM? Aside from it being a disaster performance-wise, the memory bus was clocked at 133MHz, while the P4's FSB was clocked at 400MHz (100MHz x 4). That's just one example.
Because of latency, you usually want the FSB and memory bus to match. But the point is that it doesn't have to match...
~cdogg
[tab]"The secret to creativity is knowing how to hide your sources"
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