Conversion program

[py]

Hi,<br>
I am currently writing a program to convert Verilog to VHDL using perl. Does anyone know how to get perl to pull certain words out of a string.<br>
EG.<br>
std_ulogic anyword [31:24;;<br>
<br>
I need to pull anyword from the string and write it to a file.<br>
Any help would be greatly appreciated.

 

[MikeLacey]

Perl's ok at that sort of thing - but I have to admit I don't understand your example. Say it a different way would you?<br>
<br>
Mike<br>
<p>Mike Lacey<br><a href=mailto:Mike_Lacey@Cargill.Com>Mike_Lacey@Cargill.Com</a><br><a href=

http://www.cargill.com/>

Cargill's Corporate Web Site</a><br>

 

[goBoating]

Perl has strong regex capabilities- but I have to admit I don't understand your example.<br>
Say it a different way would you?

 

[py]

Sorry ,looking at it now that example is awfull. The following is an example of what I need to convert.<br>
This=&gt; input [31:24] rgf_bd_addr;<br>
input rsm_vld_bit;<br>
output r_data; <br>
<br>
To This=&gt; rgf_bd_addr : in std_ulogic_vector(31downto24);<br>
rsm_vld_bit : in std_ulogic;<br>
r_data : out std_ulogic;<br>
Mike has been of great help with the output stuff so far, He produced the following code which works.<br>
#!/usr/local/bin/perl<br>
while(&lt;&gt{<br>
if(/^\s*output\s+(.*);\s*$/){<br>
print &quot;$1\t: out std_ulogic;\n&quot;;<br>
}<br>
}<br>

 

[py]

Here is Mikes solution to the problem which works really well.<br>
<br>
#!/usr/bin/perl<br>
while(&lt;&gt{<br>
if(/^\s*output\s+(.*);\s*$/){<br>
print &quot;$1\t: out std_ulogic;\n&quot;;<br>
}<br>
if(/^\s*input.+(..)..)]\s*(.*);\s*$/){<br>
print &quot;$3\t: std_ulogic_vector ($1 downto $2);\n&quot;;<br>
}<br>
}