Are there known problems with inout port assignements? 1

[Mariskahime]

I would like to ask, if there are known problems with value assignements to the inout port of std_logic_vector type. (From IEEE.std_logic_1164). My program seems to work correctly, but when I try to assign a value to the port (for example Data <= "ZZZZZZZZZZZZZZZZ"; ) it just doesnt work and the signal stays at "UUUUU...". Thank you

 

[jeandelfrigo]

Mariskahime,

Normally with inout ports you have an extra output enable signal.

Data <= signData when OE = '1' else "ZZZZZZ";

The input part of an inout you can read like a normal input.

Now personally I have also set inout ports to fixed high impedant values and I have never had any problems with that.

Now the UUUUU you get is from simulation I think.

Simulation requires your code to get a certain reset, so that all singals and ports get a defined state.

So you can either add an dedicated reset to you code or you can do this little tric.

In the declaration of your port add the following.

Data : std_logic_vector(7 downto 0) := (others => '0');

It's the last part that tells the simulator what the initial value should be.

You can do the same thing for internal signals in their declaration.

The synthesis tool will ignore this, although XST for Xilinx will, for internal signals only, use this to determine the reset condition if no other conditions are found in the code.

regards

jeandelfrigo