Hi everyone!
I know that vhdl can model a RAM memory, but I need a ROM memory, could I do something like a ROM memory?
I've been reading the datasheet of my cpld CY7C372i but it just says about logic blocks and macrocells, doesn´t tell me if I can´t do a ROM memory.
any help would be appreciated.
Hi everyone!
I've been reading other posts about modeling clock in vhdl, now:
1. i see that delays are just for simulations, not for physical implementations
2. same for falling and rising edge triggers in same process
are this points correct?
i've tried too, to make a frecuency multiplier...
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