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We can use a dll to multiply or divide a clock in virtex or spartan(I am not very sure about spartan) by multiples of 2 to 32 as said in the Xilinx online application notes. getting a double or four times multiple is easy but I need a 1.5 times clk. I can use a 32 Mhz but its multiple is 0.75...

guys I m using the following code to generate a 24MHZ clock from a 16Mhz clock but I do not get the desired clock. Can anyone tell me why?? (Clk_in is a 16Mhz clk) library.... .... entity clk3x is port (CLK_IN, RST_DLL : in std_logic; CLK24Mhz, LOCKED : out std_logic); end clk3x...

Thanks dude I did it by reducing logic. Luckily I was not over by much so could resolve by removing some unnecessary logic.

Hey guys I am getting the error that the design is too large to fit in the device(Xilinx webpack and I am using Spartan-II). In the Design details I see the number slices is 1211/1200 and I have like 124 slices of unrealated logic. I would like to know if there is a way we can increase the size...

I tried IBUFG too but it is not working. I had two signals giving the same error message. I used a dummy signal to reroute the clk and got rid of one error but the other still keeps coming.

hey guys I am using project navigator and I get the following error in the translation report ERROR:MapLib:93 - Illegal LOC on symbol "fpga_cclk" (pad signal=fpga_cclk) or IBUFG symbol "fpga_cclk_ibufg" (output signal=fpga_cclk_ibufg), IPAD-IBUFG should only be LOCed...

Thanks for the help dude. You are right I am using Modelsim. I too thought of the same thing from the manual where is says we can use the waveform to view and read but was not sure if we can use it as input. Well if u come up with something let me know.

Hey guys I need to use the output of a testbench as an input to another. I mean if I generate a waveform from one testbench, can it be used as an input to another module at a later time? Or in other words can I save a waveform and use it later as an input signal for another program?

All right guys got it don't wory abt it

how do I select the top module? like for exampleif I already have a project counter_top | |--tb_counter |--counter_1 |--counter_2 how do I insert a vhd file counter_3 between counter_1 and counter_2 such that it comes like this counter_top |...

No its ok I got it. my bad I didn't define reset. Thanks a lot dude.

Yes I tried that but I don't know why it didn't work. What I earlier tried was wait until clk' event and clk ='1'; if rst = '1'then count <= &quot;000&quot;; DSP_TOSC_INTV <= '0'; DSP_RESET <= '0'; else count <= count + 1; if count = &quot;111&quot; then DSP_RESET <= not...

How can I add a new vhdl file to an existing project(Xilinx project navigator) such that it is nested inside one of the module?

Hey guys I need to generate a signal that is low for 8 clk cycles and then high for 8 clk cycles. Which is the shortest way to code for this.