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By the way, it is usually considered bad design practice, to assign the same signal in two different processes, even if it does not give an error

Correct me if I am wrong. I believe that you can assign std_logic signals in different processes. However, for example, if one process assigns a '1', and the other assigns a '0' at the same time, the result will be 'X'. There is a table somewhere that goes through all the results from the...

Hi all, I have designed a user peripheral to connect via an OPB Bus to a MicroBlaze processor. Also, an interrupt controller is connected to the OPB Bus. My user peripheral generates two interrupts, which connect to the interrupt controller. The interrupt controller irq then connects to the...

XST (in Xilinx ISE) tracks all the clock frequencies. Some of my core uses 100MHz, some uses 200MHz. The timing constraints reported are for the top level (i.e. the input clock). Therefore the max frequency for the input is 105MHz, and theoretically, 210MHz for the doubled clock. But I don't...

I had this discussion already. Look here, it may help http://www.tek-tips.com/gviewthread.cfm/lev2/4/lev3/32/pid/284/qid/668695

Hi, I am doing a project that uses a 100MHz clock. Within the project I use two DCMs, one to double the clock to 200MHz, and another to double and phase shift the clock. When I run XST on the project, It tells me that the max frequency is ~105MHz, which is good for me, as it is over 100MHz...

Ok. Say there were two processes PR1: process(clk,rst) begin if rst = '1' then .... elsif clk'event and clk = '1' then .... if a >= 16 then .... end if; .... end if; end process; PR2: process(clk,rst) begin if rst = '1' then .... elsif clk'event and clk...

Just a thought, The DLL input frequency range is 24 -> 326 MHz. 16 MHz falls short of this. Try using the 32 MHz frequency, and set the divide attribute to 4 and the multiply attribute to 3. Ciarán Hughes

sheenjrg, Try setting the DFS_FREQUENCY_MODE attribute to LOW. attribute DFS_FREQUENCY_MODE : string; attribute DFS_FREQUENCY_MODE of U2 : label is "LOW"; If this doesn't work, try set it to HIGH. I don't know what the default is. Ciarán Hughes

Which of the following synthesises to more efficient code? process(clk,rst) begin if rst = '1' then .... elsif clk'event and clk = '1' then if a >= 16 then .... end if; end if; end process; OR aGTEq16 <= '1' when a >= 16 else '0'; process(clk,rst) begin if rst = '1'...

That's where good documentation comes in. It's a shame not to implement the faster option because of readability (especially in a language like VHDL). I tend to use comments within the code to fully document all that is going on.

I fixed the problem by using logic gates e.g. val[3] <= input(9) or input(8) or input(7); val[2],val[1] and val[0] got more complex, but it fixed the timing problems. I don't know, is it better to use logic gates than select statements? Ciarán

Hi all. In part of my code, I have the following val <= &quot;1010&quot; when input(9) = '1' else &quot;1001&quot; when input(8) = '1' else &quot;1000&quot; when input(7) = '1' else &quot;0111&quot; when input(6) = '1' else &quot;0110&quot; when input(5) = '1' else...

Thanks guys. This is a real pain in the ass. I'm probably going to have to break this thing right down, and come up with new logic.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity entropyHuffman is port( clk, rst, go, eob: in std_logic; zrl, cat: in std_logic_vector(3 downto 0); addBits: in std_logic_vector(10 downto 0); rfd, done, rdy: out std_logic; dout: out std_logic_vector(31...

That should be zeros - 16 (not zeros - 1)

Or perhaps [code]if zeros >= 16 then zrlBuf(count1) <= X&quot;F&quot;; catBuf(count1) <= X&quot;0&quot;; count := count + 1; zeros := zeros - 1; end if; if zeros >= 16 then zrlBuf(count1) <= X&quot;F&quot;; catBuf(count1) <= X&quot;0&quot;; count := count + 1; zeros := zeros -...

I do have an 255 element array of std_logic_vector(15 downto 0). Could that be causing the problem? Would I be better to use a ROM block?

I am trying to code a JPEG encoder in VHDL. One of the stages of JPEG encoding is Zero Run Length Encoding, where the number of zeros before a non-zero value is counted, and then stored as a 4-bit unsigned integer, followed by the four bits that are the non-zero value. e.g. 1 0 0 0 0 3 0 0 0 0...

Hi all, When I try to synthesise some vhdl code in my project in Xilinx ISE, I get the following error ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 2064200 kb..... It only happens with a couple of my designs...