Search results for query: *

You could just use generate to that to. simply a for-generate loop would do that. (I hope I have understood what your problem is.)

Something usually done in such situations is, look for signals you think may have caused the problem, and extract them, i.e. assign them to ports, just to see whta happens to them.

Just explain a little more. Do you want to inverse a given digital filter, using your FPGA? or is it something else?

And I should say that this doesn't use too much logic, although not little either: Length= 32 bit : Number of SLICES : 81; Clock Frequency : 131.70 MHz Length=16 bit : Number of SLICES : 43; Clock Frequency :143.37 MHz (I think the algorithm iterates the number of bits of each...

for synthesizing trigonometric functions, there are two ways. the first is large-enough lookup tables (if it doesn't get too big). The second is algorithms named CORDIC. I have read about it, but don't know it exactly. However I know it works, and is reasonable. It could be pipelined or iterated.

And I should say that this doesn't use too much logic, although not little either: Length= 32 bit : Number of SLICES : 81; Clock Frequency : 131.70 MHz Length=16 bit : Number of SLICES : 43; Clock Frequency :143.37 MHz (On a Spartan II)

There are not-so-hard algorithms for implementation. the best is the non-storing recursive algorithm. have a look at this: http://www.cp.eng.chula.ac.th/~krerk/publication/iscit-sqrt.pdf

I don't know exactly what this error means, but I think you should first convert the std_logic_vector to unsigned or signed, and then to integer. this needs the std_logic_unsigned and std_logic_signed libraries to be defines (with USE). I have always done it that way, and never have encountered...

A signal cam't be assigned in two processes. that's one basic rule in VHDL. This means that the way you acted for initialization, not only doesn't do your job, but denies the RAM from working properly. you'll never be able to put something in it, and you'll get X whenever you try to. In fact the...

I am not sure if you are using 2's complement or not. if so, and the input is all fractional (with one sign bit) in the accumulator the 9 msb bits will be integers. after the multipliaction, the result is 44 bits, and if again the coefficient has 1 sign bit, there will be 10 msbs as integers...

I don't see much difference. I think he synthesizer will be able to optimize this amount of difference to the best. If not, of course the second is worse because of presence of 2 comparators (one equal to/greater than, the other equal to)

Hi It's very simple. You are driving a signal both in your testbench and in the process in the core. That always will cause congestion and so results in X's. Solution is simple too. When in one of the two statements is to be perofrormed, (and the other is of course not to be active at the same...

I'm pasting it from a PDF file which is available online at http://www.engr.mun.ca/~theo/Courses/fm/pub/fm13sl.pdf it's a psuedo code which could be written in VHDL very easily. I have written the VHDL code just form this, but I don't have it now. /* do [q := a div b] by */ { q = 0 ; int e = b...

Hi it's simple. you are driving the port R both in the testbench and in the inner process. When you intend just one of these you should assign it all z (others =< 'Z')in the other statement. (for example when you want to read from this port, do this in the testbench)

Hi. It depends on the FPGA you use. in Xilinx, you could use a XC95xx with at most 10-20 MHz, while Spartan is about 100 MHz, Virtex upto about 300 MHz, and even more with Virtex II & Virtex II Pro. (I am sure the device works this fast, but maybe even more).

I'm not so familiar with VHDL for modeling, but I'm sure your code is wrong for synthesis. In synthesis, the if-generate statement must have a condition which is computable for the simulator/synthesizer. In fact it should not contain a condition based on a signal. usually the If-generate...

for any trigonometric function in synthesis you could use CORDIC algorithm. I myself have not used it but i know it does the job well. for more info search internet and you'll find a lot; or contact me and I can send you some articles

hi I want to implement a simple dual-port ram in VHDL by Webpack as a BlockRAM on a SPARTANII. but the tool says you're using your ram in a non-supported mode and so implements it as distributed ram. how should the ram be written to solve the problem?

The write code would be : DOUT <= DIN(7) & DIN(7) & DIN(7) & DIN(6 downto 2) This way you'll keep the sign.

hello all. i want to instantiate lots of -say 500- instances of a component. could it be done by a for-generate loop? i have problem with labelling the instances in the loop. any solution?