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VHDL synthesis problem
Hi all, I have written a small piece of code in an attemt of learining VHDL. The code is a first step in the implementation of a UART transmitter. The code compiles and simulates OK, but when I try to implement the design (using the webpack from XILINX, for a CoolRunnerII CPLD), I get the...- brumbarchris
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- Forum: VHDL
