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  • Users: mat615
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  1. mat615

    'EVENT ERROR IN IF STATEMENT

    I'm using Quartus to compile a DFLIPFLOP that i had created originally for Modelsim Altera, on the Modelsim it compiles great with no error on Quartus II i get the following error: Error: VHDL Case Statement or If Statement error at DFLIPFLOP.vhd(22): can't synthesize condition that contains an...
    • mat615
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    • Replies: 2
    • Forum: VHDL

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