Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations Chriss Miller on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Search results for query: *

  • Users: JayHandle
  • Content: Threads
  • Order by date
  1. JayHandle

    out vs buffer & package vs. components

    Hello, Can someone please recommend when to use buffer vs. out mode and when to use packages vs. component instantiation? I'll be working on a reasonably large project with 2 other students, and we need to get the software engineering aspects of VHDL down pat. -james
  2. JayHandle

    Simple Problem: i/o declaration error

    Hello, I'm just learning about VHDL components and I'm having a problem with the i/o ports being undeclared in the top level of the hierarchy. Synopsis vhdlan compiles the program perfectly, but vhdldbx (the debugger/simulator) will state that the port names are undeclared the second time I...

Part and Inventory Search

Back
Top