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- Users: spidermanvenom
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convert the clock signal into 50% duty cycle
Hallo everyone! Regarding on my project, I'm still doing the design for frame grabber board. As I have an input clock signal which is greater than 50% duty cycle, I need to convert it into 50% duty cycle. I do not know how to implement it in VHDL program. If someone knows how, please teach me...- spidermanvenom
- Thread
- Replies: 3
- Forum: VHDL
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how can i determine the frequency of a clock output?
Hallo everyone, I'm doing my project about camera link, and i need to know the code on how to determine the frequency of a clock. the output of the camera goes to the ALTERA PLD. Thanks! c",)-- spidermanvenom
- Thread
- Replies: 12
- Forum: VHDL
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same frequency but different duty cycle
To everyone, I am programing a VHDL for PLD. Does anyone knows the code or algorithm of generating a new clock with a different duty cycle from a given clock. (For example, the given clock 50MHz has a 50% duty cycle, the output clock should have 50 MHz too but with 85% duty cycle. Thanks!- spidermanvenom
- Thread
- Replies: 8
- Forum: VHDL
