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Problem adding two integers
Hi, I am trying to add an integer to an integer variable in VHDL, but when I try to synthesise it in XST I get: "ERROR:Xst:1549 - controller.vhd line 331: Range bound must be a constant." I have a bus (7 downto 0) that I convert to an integer using CONV_INTEGER, then try to add it... -
Problem with simple(ish) counter
Hi, I am trying to synthesise the following VHDL description of a 16-bit counter using XST (in Xilinx ISE Webpack), but I am getting a synthesis error - "Bad synchronous description" on signal 'tmpcount'. Could anyone please give me a clue as to where I have gone wrong? Thanks... -
Trying to synthesise FSM
Hi, I am currently developing an 8-channel event logger in VHDL to replace an existing 8051 assembly routine that is too slow. When completed, the PLD will interface with the 8051, which will pass commands over a bus and expect the logger to respond with the timer values that it has logged for...
