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coding help
guys I m using the following code to generate a 24MHZ clock from a 16Mhz clock but I do not get the desired clock. Can anyone tell me why?? (Clk_in is a 16Mhz clk) library.... .... entity clk3x is port (CLK_IN, RST_DLL : in std_logic; CLK24Mhz, LOCKED : out std_logic); end clk3x... -
Hey guys I am getting the error tha
Hey guys I am getting the error that the design is too large to fit in the device(Xilinx webpack and I am using Spartan-II). In the Design details I see the number slices is 1211/1200 and I have like 124 slices of unrealated logic. I would like to know if there is a way we can increase the size... -
Illegal LOC on symbol ...LOCed to GCLKIOB site
hey guys I am using project navigator and I get the following error in the translation report ERROR:MapLib:93 - Illegal LOC on symbol "fpga_cclk" (pad signal=fpga_cclk) or IBUFG symbol "fpga_cclk_ibufg" (output signal=fpga_cclk_ibufg), IPAD-IBUFG should only be LOCed... -
Using wlf as input
Hey guys I need to use the output of a testbench as an input to another. I mean if I generate a waveform from one testbench, can it be used as an input to another module at a later time? Or in other words can I save a waveform and use it later as an input signal for another program? -
Adding Source
How can I add a new vhdl file to an existing project(Xilinx project navigator) such that it is nested inside one of the module? -
Clock help
Hey guys I need to generate a signal that is low for 8 clk cycles and then high for 8 clk cycles. Which is the shortest way to code for this.
