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Hi all, I have designed a user peripheral to connect via an OPB Bus to a MicroBlaze processor. Also, an interrupt controller is connected to the OPB Bus. My user peripheral generates two interrupts, which connect to the interrupt controller. The interrupt controller irq then connects to the...

Hi, I am doing a project that uses a 100MHz clock. Within the project I use two DCMs, one to double the clock to 200MHz, and another to double and phase shift the clock. When I run XST on the project, It tells me that the max frequency is ~105MHz, which is good for me, as it is over 100MHz...

Which of the following synthesises to more efficient code? process(clk,rst) begin if rst = '1' then .... elsif clk'event and clk = '1' then if a >= 16 then .... end if; end if; end process; OR aGTEq16 <= '1' when a >= 16 else '0'; process(clk,rst) begin if rst = '1'...

Hi all. In part of my code, I have the following val <= &quot;1010&quot; when input(9) = '1' else &quot;1001&quot; when input(8) = '1' else &quot;1000&quot; when input(7) = '1' else &quot;0111&quot; when input(6) = '1' else &quot;0110&quot; when input(5) = '1' else...

Hi all, When I try to synthesise some vhdl code in my project in Xilinx ISE, I get the following error ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 2064200 kb..... It only happens with a couple of my designs...

Hi all, Can anyone tell me why, when I add signals to the waveform viewer window in Modelsim (as in add->wave->signals in region, or if i drag and drop), Modelsim closes itself? Thanks

Is there any operator to divide a [code]std_logic_vector[\code], either by another [code]std_logic_vector[\code] or by an [code]integer[\code]? I am using the following code at the moment [code]temp := CONV_INTEGER(buf2) / q ; ZRLOut <= CONV_STD_LOGIC_VECTOR(temp,11);[\code] where...

Hi all. I have a vhdl module which works fine under behavioural simulation, and even under post-translate simulation. But when I try a post-map simulation, I get the following error: [code]# ** Warning: */X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.34 ns; Observed :=...

Anybody know any good opensource web pages for VHDL core? Specifically, I am looking for JPEG related stuff (DCT, Quantization, etc.) Thanks all.

I have WinME on my Advent Laptop, and the clock (as in the bottom right of the screen when WinME has booted) keeps resetting the year to 2000. Why? It's annoying, because it means I have to change it every time I turn on the Laptop (It messes with some of my application licenses).

I have the following in my code: [code]OUTPUT: if ND = '1' and RDY = '0' generate begin DOUT0 <= (&quot;00&quot; & DIN0) + (&quot;00&quot; & DIN7) - &quot;0100000000&quot;; end generate OUTPUT;[\code] However, when ND and RDY are the appropriate values, the statement doesn't execute. Any...

Hi. The line below is causing me problems. [code]DOUT <= DIN0 + DIN1;[\code] DIN0 and DIN1 are inputs to the entity of type std_logic_vector(7 downto 0), and DOUT is an output of the entity of the type std_logic_vector(8 downto 0). The problem is that the buses are of different width, and...