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  • Users: aalbert
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  1. aalbert

    VHDL and Verilog using Sinplify

    Hi everybody ! I've got a problem using Sinplify, and my instructor can't help me ! I try to synthetise a project with a top VHDL file which uses 2 components. The architecture of these components was synthetised in .vqm files (verilog quartus map) but when I synthetise the whole project...
  2. aalbert

    Compiling VHDL librairies

    Hi ! I'm working on a huge VHDL project, and I want to use librairies to manage it simplier. I seen it's possible to group multiple VHDL files in one library. Is it possible to compile these VHDL files into a single library file ? And after use only this library file ? (I want to make...

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