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  • Users: avib
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  1. avib

    COS & SIN functions in VHDL

    Hi, Does anybody know how to implement cos/sin functions in VHDL. Or even better, is there any on the shelf IEEE cos/sin functions? Thanks
  2. avib

    Altera's ByteBlaster II

    Hi, I'm intending to use Altera's EPCS4 serial configuration device and i noticed that it requires a new configuartion cable (ByteBlaster II). The old configuration cable (ByteBlasterMV) data sheet included a schematic of the cable. ByteBlaster II data sheet is missing the electrical schematic...
  3. avib

    KMODE_EXCEPTION_NOT_HANDLED

    My computer became to be very wierd in the last fiew days: I upgraded my HD from 10G to 40G and I noticed that the CPU is almost 100% used even in Idle operation (described in another thread). After that my CD-R/RW stoped working. It was recognised in the BIOS and in the task manager but when I...
  4. avib

    100% use of CPU after Hard Disk Replacement

    Hi, I replaced my hard disk to MAXTOR 40.0GB DiamondMax Plus 8 ULTRA ATA133 IDE 7200RPM. I use Pentium 4 1.6GB and Win2000. Since i replaced my hard disk my computer is very very slow. When I open the task manager I can see that the CPU is 100% used and the processes that uses it are software...
  5. avib

    Hi, I replaced my hard disk to MAX

    Hi, I replaced my hard disk to MAXTOR 40.0GB DiamondMax Plus 8 ULTRA ATA133 IDE 7200RPM. My OS is Win2000. Since i replaced my hard disk my computer is very very slow. When I open the task manager I can see that the CPU is 100% used and the processes that uses it are software that usualy don't...
  6. avib

    Implementing fuse by using small trace width

    Hi, I'm implementing a board that will have two external lines.this two lines will be connected to a mosfet which will behave as a switch to connect between them. the maximum current that I allow on the lines is 1A. I want to put a protection on the traces by using a fuse, but I don't want to...
  7. avib

    Initialization

    Hi, I'm using Altera's Acex device and I have a problem: My design don't use reset signal so I can't initialize the internal signals and registers. when I simulate it I don't have any problem (because I initialize the signals when I declare them) but when I Synthesize it (Synplicity) and then...
  8. avib

    negative integer and vector multiply

    Hi, I'm trying to do multiplication between a negative integer and a vector and I'm getting errors what is wrong with this code (this is only a part of it) thanks, Avi LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all ; ENTITY example IS PORT( clk...
  9. avib

    Synchronizing two clocks

    Hi, I have FPGA with two clocks, one is 40Mhz and the other is 33Mhz. Some of the logic signals are sampled by the 33Mhz clock and then connect to another logic that uses the 40Mhz clock. What is the best way of synchronizing these signal to the 40Mhz clock? thanks, Avi

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