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BlockRAM in VHDL
hi I want to implement a simple dual-port ram in VHDL by Webpack as a BlockRAM on a SPARTANII. but the tool says you're using your ram in a non-supported mode and so implements it as distributed ram. how should the ram be written to solve the problem? -
multiple component instantiation
hello all. i want to instantiate lots of -say 500- instances of a component. could it be done by a for-generate loop? i have problem with labelling the instances in the loop. any solution? -
clock phase synchroniztion
is there any way to find the exact clock edges of a data stream, and generate such a clock? we know the frequency of the tx and know we want to have a clock exactly synchronized in the rx. any solution in VHDL? -
asynchronous FIFO
hello I have a design in which data comes in in a stream, but shoul be put in packets with headers, so i need a fifo. the input and output frequencies are different and his makes problem in distinguishing full and empty states. any answer?
