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What's wrong witht that code?
someone please tell me what's the problem with the code? TAI ------------------------------------------------------------ entity switches is port( clock : in std_logic; Switches : in std_logic_vector ( 3 downto 0); output: out std_logic_vector (7 downto 0) ); end switches; architecture... -
OBUFDS or OBUFDS_LVDS ?? plz help me about differential signal
hi, I need to use [LVDS(350 mV)] differential signal input/output at my project . But I have no experience about using differential signal, do I need to use OBUFDS or OBUFDS_LVDS component ??? I'd be grateful if u give me very little example of usage of this components. Thanks in advance... -
VHDL - synthesized error, please help me out!!
hi, when the code is synthesized, I got the error below: ERROR:Xst:827 - "C:/Xilinx92i/timer.vhd" line 19: Signal cntr cannot be synthesized, bad synchronous description. would you please check my short code and tell me why do I encounter such a error ? thanks in advance...
