hi there, am trying to synthesis a generic clock divider I have created. it works fine in simulation with modelsim but xilinx syntheses tool xst is not happy. - see code below:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity generic_clk_divider is
generic
(...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.