Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations TouchToneTommy on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Search results for query: *

  • Users: DrFuzzy
  • Content: Threads
  • Order by date
  1. DrFuzzy

    Beautification Script - Regular Expressions

    Hi all, I am working on a VHDL code beautifier with Perl. I've come to this part of the beautification process and I got really stuck. Assume for example the following piece of VHDl code: entity JK_FF is port( clock : in std_logic; J, K : in std_logic; reset : in std_logic...

Part and Inventory Search

Back
Top